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S3F49FAX
for Compact Flash
SPECIFICATION
Revision 1.0
HELP DESK Sejin, Ahn (herlock@sec.samsung.com) Sanghun, Song (hoontour@samsung.com)
SPECIFICATION
S3F49FAX
Table of Contents
1.1 1.2 1.3 2.1 2.2 Introduction ..............................................................................................................................2 Features...................................................................................................................................3 Block Diagram .........................................................................................................................4 Controller Package Drawing....................................................................................................5 Controller Pin Assignments and Pin Type ...............................................................................6
Table of Figures
1 2 3 S3F49FAX Block Diagram.......................................................................................................4 S3F49FAX Pin Assignment .....................................................................................................5 100-TQFP-1414 Package Dimension......................................................................................26
Table of Tables
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 100-Pin TSOP Pin Assignment ...............................................................................................6 I/O Type Description ................................................................................................................10 Signal Description for PCMCIA/IDE Interface .........................................................................11 Signal Description for Flash Memory Interface .......................................................................17 Signal Description for Miscellaneous Part ...............................................................................20 Signal Description for Power Signal ........................................................................................21 Signal Description for USB Device ..........................................................................................21 Signal Description for Internal NOR Flash Memory ................................................................21 Absolute Maximum Ratings.....................................................................................................22 Recommended Operating Conditions .....................................................................................22 Thermal Characteristics...........................................................................................................22 D.C. Electrical Characteristics (In case of 3.3V Interface I/O) ................................................23 D.C. Electrical Characteristics (In case of 5.0V Interface I/O) ................................................24 System Clock Timing ...............................................................................................................25 POR(power on reset) Detection Level.....................................................................................25
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SPECIFICATION
S3F49FAX
1.1 INTRODUCTION
Samsung's S3F49FAX is NAND flash memory controller which can control flash memories as solid state disk. It provides PC Card ATA/IDE/USB interface, host and flash transfer rates up to 20.0MB/S. S3F49FAX can control flash memory maximum 8 pieces. The device is designed using 0.35um CMOS process, assembled as 100-TQFP package. It supports operation in both 5.0V and 3.3V. An outstanding feature of the S3F49FAX flash disk controller is its CPU core: the ARM7TDMI 16/32-bit RISC processor, designed by Advanced RISC Machine (ARM), Ltd. The ARM core is a low-power, general purpose, microprocessor macro-cell that was developed for use in application-specific and customer-specific integrated circuit. It is simple, elegant, and fully static design is particularly suitable for cost and power sensitive application.
* * * * * * * * * * *
PC Card-ATA/True IDE/CompactFlash/USB compatible host interface Automatic sensing of PC Card ATA and IDE Full Speed USB Function Controller compatible with the USB Specification Version 1.1 Included 256-byte CIS RAM Five PC Card ATA addressing modes Host data transfer rate: 20MB/s Flash data transfer rate: 20MB/s (It depends on the characteristics of flash memory) Host Interface: 8/16-bit Access Flash Interface: 8-bit Access Support 3 power save mode: SLEEP/ACTIVE mode (Auto power down function) Support 128/256/512Mbit, 1Gbit, 2Gbit, 4Gbit NAND flash memory made by Samsung NAND Flash Density 128M/256M/512M/1G bit (512Byte/page) 1G / 2G / 4G bit (2048Byte/page) Min. / Max. Capacity (number of flash) 16MB / 1 G Byte (Up to 8EA) 256MB / 4 G Byte (Up to 8EA)
* * * *
ECC function (Error correction algorithm): 2bit correction Available 100-pin TQFP Interface Voltage Range : 3.0 to 5.5V Interface Support Controller Part Number S3F49FAXZZ S3F49FAXZA USB 1.1 Host interface CompactFlash
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SPECIFICATION
S3F49FAX
1.2 FEATURES
Microprocessor Architecture
* * *
USB Device
*
16/32bit RISC architecture Efficient and powerful ARM7TDMI CPU core Cost-effective JTAG based debug solution
Full Speed USB Function Controller compatible with the USB Specification Version 1.1 DMA Interface for Bulk Transfer 5 Endpoint with FIFO Integrated USB Transceiver (ASIC Full speed USB Pad)
* * *
Internal Memory
* *
Included 48KB internal NOR FLASH Included 16KB internal SRAM
DMA Controller
* * * *
ECC Engine
*
Two-channel,general-purpose DMA controller Data transfer between SRAM and Flash, SRAM and USB without CPU Intervention Support for 8/16/32bit data transfers Increment or decrement of source or destination address
Correct 2-bit Error
64bit Counter
*
64bit timer by cascading the 32-bit timers.
Interface Voltage Range
*
3.0 to 5.5 volts
Programmable Timer
*
Package Type
*
channel 16bit programmable timer
100-TQFP
Interrupts
* *
8 interrupt sources Normal or fast interrupt modes (IRQ, FIQ)
PC-Card/ATA Interface
* * *
Include 256Bytes SRAM for CIS Support memory and I/O addressing mode Support True IDE mode
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SPECIFICATION
S3F49FAX
1.3 BLOCK DIAGRAM
NAND FLASH
USB Host
LocalBUS ARM7TDMI NOR FLASH (48KB) BUS CNTL
USB Device FLASH Controller CF Host PCMCIA IDE SFR for ECC/FTL ECC Engine 64bit Counter SRAM (16KB) ARBITER 16bit TIMER Reset CNTL Power MAN
DMA0
DMA1
POR
PLL
VCO
Figure 1. S3F49FAX Block Diagram
4
S3F49FAX
BVD1/XSTSCHG
XWP/XIOIS16
BVD2/XDASP
VDD6
VDD5
-FWP
-FWE
XD10
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
-XREG PVDD1 XA1 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 XA9 PVDD2 -XIORD -XOE XA10 -XCE2 -XCE1 XD15 93 94 95 96 97 98 99 100 10 -XINPACK XA2 -XWAIT XA3 XRESET XA4 XA5 -XCSEL/XDS XA6 XRDY XA7 -XWE 77
76
51
-FRE
GND
GND
XD0
XD1
XD8
XD2
XD9
XA0
FD7
FD6
FD5
FD4
FD3
FD2
FD1
FD0
50
FALE
49
FCLE
48
VDD4
47
GND
46
FRDY1 / SDATA
45
FRDY0 / SCLK
44
FCE0
43
FCE1
42
FCE2 / GPIO[0]
41
FCE3 / GPIO[1]
40
FCE4 / GPIO[2]
39
FCE5 / GPIO[3]
38
FCE6 / GPIO[4]
37
FCE7 / GPIO[5]
36
FCE8 / GPIO[6]
2.1 CONTROLLER PACKAGE DRAWING
PIN INFORMATION
XA8 -XIOWR
35
FCE9 / GPIO[7]
34
VDD3
33
TEST2
32
TEST1
31
TEST0
30
VCON
29
MODE_SET
28
VSSA
27
PLLCAP
26 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9
VDDA
SPECIFICATION
VDD1
VDD2
GND
GND
DP
TMS
XD7
XD6
XD5
XD4
XD3
XD14
XD13
XD12
XD11
TCK
XIN
DN
-TRST
XOUT
TDI
TDO
GPIO[9] / CKOUT
2
GPIO[8] / RSOUT
HWP
25
Figure 2. S3F49FAX Pin Assignment
S3F49FAX 100TQFP
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SPECIFICATION
S3F49FAX
2.2 CONTROLLER PIN ASSIGNMENTS AND PIN TYPE
Table 1. 100-Pin TSOP Pin Assignment Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name XD7 XD14 XD6 XD13 XD5 XD12 XD4 XD11 XD3 GND DP DN VDD1 -TRST TDI TMS TCK GND VDD2 TDO XIN XOUT HWP CKOUT / GPIO[9] RSOUT / GPIO[8] I I/O I/O I/O State I/O I/O I/O I/O I/O I/O I/O I/O I/O P I/O I/O P I I I I P P O pob4 psoscm26 psoscm26 pic pbct4 pbct4 pis pis pis pis pbusb1 pbusb1 I/O Type pvbct83 pvbct83 pvbct83 pvbct83 pvbct83 pvbct83 pvbct83 pvbct83 pvbct83 Function Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Ground Positive data for USB Negative data for USB Power Test reset for JTAG Test data input for JTAG Test mode select for JTAG Test clock for JTAG Ground Power Test data output for JTAG Crystal Input Crystal Output Disable write command Output of Clock signal / General I/O pin Output of Rest signal / General I/O pin
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SPECIFICATION
S3F49FAX
Table 1. 100-Pin TSOP Pin Assignment (Continued) Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Pin Name VDDA PLLCAP VSSA MODE_DET VCON TEST0 TEST1 TEST2 VDD3 FCE9 / GPIO[7] FCE8 / GPIO[6] FCE7/ GPIO[5] FCE6/ GPIO[4] FCE5/ GPIO[3] FCE4/ GPIO[2] FCE3/ GPIO[1] FCE2 / GPIO[0] FCE1 FCE0 FRDY0 / SCLK FRDY1 / SDATA GND P I I I I I P I/O I/O I/O I/O I/O I/O I/O I/O O O I I/O P pbct4sm pbct4sm pbct4sm pbct4sm pbct4sm pbct4sm pbct4sm pbct4sm pob4sm pob4sm Picu Pbcut4 pic pica pic pic pifsn I/O State P apad_80 I/O Type Function Analog Power for PLL Capacitor for PLL Analog Ground for PLL Select Interface Mode Reference Voltage for VCO Select test mode Select test mode Select test mode Power Enable 9 chip of nand flash / General I/O PIN Enable 8 chip of nand flash / General I/O PIN Enable 7 chip of nand flash / General I/O PIN Enable 6 chip of nand flash / General I/O PIN Enable 5 chip of nand flash / General I/O PIN Enable 4 chip of nand flash / General I/O PIN Enable 3 chip of nand flash / General I/O PIN Enable 2 chip of nand flash / General I/O PIN Enable 1 chip of nand flash Enable 0 chip of nand flash Ready/Busy signal of nand flash / Serial data for internal flash Ready/Busy signal of nand flash / Serial clock for internal flash Ground
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SPECIFICATION
S3F49FAX
Table 1. 100-Pin TSOP Pin Assignment (Continued) Pin No. 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name VDD4 FCLE FALE -FRE -FWE -FWP VDD5 FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 GND VDD6 XD10 XWP / IOIS16 XD9 XD2 XD8 XD1 BVD1 / XSTSCHG XD0 BVD2 / XDASP XA0 GND I/O State P O O O O O P I/O I/O I/O I/O I/O I/O I/O I/O P P I/O O I/O I/O I/O I/O I/O I/O I/O I P pvbct83 pvot83 pvbct83 pvbct83 pvbct83 pvbct83 pvbcut43 pvbct83 pvbcut43 pvic3 pbcdt4 pbcdt4 pbcdt4 pbcdt4 pbcdt4 pbcdt4 pbcdt4 pbcdt4 pob4sm pob4sm pob8 pob4 pob4sm I/O Type Power Command latch enable in nand flash Address latch enable in nand flash Read enable in nand flash Write enalbe in nand flash Write protect in nand flash Power I/O of nand flash memory I/O of nand flash memory I/O of nand flash memory I/O of nand flash memory I/O of nand flash memory I/O of nand flash memory I/O of nand flash memory I/O of nand flash memory Ground Power Data bus of PCMCIA IOIS16 of PCMCIA (XIOSI16) Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA Data bus of PCMCIA STSCHG of PCMCIA (XIOIS16) Data bus of PCMCIA DASP for IDE (XDASP) Address bus of PCMCIA Ground Function
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SPECIFICATION
S3F49FAX
Table 1. 100-Pin TSOP Pin Assignment (Continued) Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name -XREG PVDD1 XA1 -XINPACK XA2 -XWAIT XA3 XRESET XA4 XA5 -XCSEL/XDS XA6 XRDY XA7 -XWE XA8 -XIOWR XA9 PVDD2 -XIORD -XOE XA10 -XCE2 -XCE1 XD15 I/O State I P I O I O I I I I I I O I I I I I P I I I I I I/O pvisu3 pvisu3 pvic3 pvisu3 pvisu3 pvbct83 pvic3 pvob43 pvic3 pvob43 pvic3 pvit3 pvic3 pvic3 pvitu3 pvic3 pvot43 pvic3 pvisu3 pvic3 pvisu3 pvic3 I/O Type pvisu3 Power Address bus of PCMCIA INPACK of PCMCIA Address bus of PCMCIA Wait signal of PCMCIA Address bus of PCMCIA Host reset signal in PCMCIA Address bus of PCMCIA Address bus of PCMCIA Master/Slave selection signal (XDS) Address bus of PCMCIA Ready/Busy signal of PCMCIA Address bus of PCMCIA Wrtie enable in PCMCIA Address bus of PCMCIA IO write signal in PCMCIA Address bus of PCMCIA Power IO read signal in PCMCIA Output enable in PCMCIA Address bus of PCMCIA Card enable 2 in PCMCIA Card enable 1 in PCMCIA Data bus of PCMCIA Function REG of PCMCIA
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SPECIFICATION
S3F49FAX
Table 2. I/O Type Description I/O Type pic picu picd pica pvic3 pvisu3 pvitu3 pvit3 pfisn_80 pob4 pob4sm pob8 pvot43 pvot83 Apad_80 Pbct4 pbcut4 pbcdt4 pbct4sm pbusb1 pvbct83 pvbcut43 psoscm26 pvob43 3.3V LVCMOS Level Input Buffers 3.3V LVCMOS Level Input Buffer with pull-up register 3.3V LVCMOS Level Input Buffer with pull-down register VCO output frequency control PAD 5V/3.3V LVCMOS Level PCMCIA Input Buffer 5V/3.3V LVCMOS Schmitt Trigger Level PCMCIA Input Buffer with Pull-up Resistor 5V/3.3V TTL Level PCMCIA Input Buffer with Pull-up Resistor 5V/3.3V TTL Level PCMCIA Input Buffer High voltage Input tolerant pad 4mA LVCMOS Normal Output Buffers 4mA LVCMOS Normal Output Buffers with Medium Slew-Rate 8mA LVCMOS Normal Output Buffers 5V/3.3V 4mA Tri-State PCMCIA Output Buffer without SRC 5V/3.3V 8mA Tri-State PCMCIA Output Buffer without SRC Analog Output for PLL capacitor 3.3V LVCMOS Level Input Buffer and 4mA Tri-State Output Buffers 3.3V LVCMOS Level Input Buffer with Pull-up Resistor and 4mA LVCMOS Tri-State Output Buffer 3.3V LVCMOS Level Input Buffer with Pull-down Resistor and 4mA LVCMOS Tri-State Output Buffer 3.3V LVCMOS level input buffer and 4mA tri-state output buffer with Medium Slew-Rate 3.3V USB differential input receiver, a differential output driver. 5V/3.3V LVCMOS Level PCMCIA Input Buffer and 8mA Tri-State PCMCIA Output Buffer without SRC 5V/3.3V LVCMOS Level PCMCIA Input Buffer with Pull-up Resistor and 4mA Tri-State PCMCIA Output Buffer without SRC Oscillator cell with enable and register 5V/3.3V 4mA PCMCIA Output Buffer witout SRC Description
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SPECIFICATION
S3F49FAX
2.3 Signal descriptions
Table 3. Signal Description for PCMCIA/IDE Interface Signal Name XA0 XA1 XA2 XA3 XA4 XA5 XA6 XA7 XA8 XA9 XA10 XD0 XD1 XD2 XD3 XD4 XD5 XD6 XD7 XD8 XD9 XD10 XD11 XD12 XD13 XD14 XD15 100-Pin Number 74 78 80 82 84 85 87 89 91 93 97 72 70 68 9 7 5 3 1 69 67 65 8 6 4 2 100 I/O I I/O Description ADDRESS BUS[10:0]: These address lines along with the -REG signal are used to select the following: The I/O port address registers within the PC Storage Card, the memory mapped port address registers within the PC Storage Card, a byte in the Card's information structure and its configuration control and status registers. This signal is the same as the PC Card Memory Mode signal in PC Card I/O mode. In True IDE Mode only A[2:0] are used to select the one of eight registers in the Task File, the remaining address lines should be grounded by the host. DATA BUS[15:0]: These lines carry the Data, Commands and Status information between the host and the controller. XDB0 is the LSB of the even byte of the word. XDB8 is the LSB of the odd byte of the word. This signal is the same as the PC Card memory mode signal in PC Card I/O mode. In True IDE mode, all Task File operations occur in byte mode on the low order bus XDB0-XDB7 while all data transfers are 16 bit using XDB0XDB15
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SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued) Signal Name 100-Pin Number I/O Description ATTRIBUTE MEMORY AREA SELECTION: This signal is used during memory cycles to distinguish between common memory and register (Attribute) memory accesses. High for Common memory, low for attribute memory. The signal must also be active (low) during I/O cycles when the I/O address is on the Bus. In True IDE mode, this input signal is not used and should be connected to VCC by the host. CARD ENABLE: These input signals are used both to select the card and to indicate to the card whether a byte or a word operation is being performed. XCE1 XCE2 99 I 98 -CE2 always accesses the odd byte of the word. -CE1 accesses the even byte or the Odd byte of the word depending on A0 and -CE2. A multi-plexing scheme based on A0, -CE1, -CE2 allows 8 bit hosts to access all data on XDB0-XDB7. This signal is the same as the PC card memory mode signal in PC Card I/O mode.In the True IDE mode, CS0 is the chip select for the task file registers while CS1 is used to select the alternate status register and the device control register. OUTPUT ENABLE: This is an output enable strobe generated by the host interface. It is used to read data from the PC Card in memory mode and to read the CIS and configuration registers. In PC Card I/O mode, this signal is used to read the CIS and configuration registers. To enable True IDE mode this input should be grounded by the host.
XREG
76
I
XOE
96
I
12
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued) Signal Name 100-Pin Number I/O Description WRITE ENABLE: This is a signal driven by the host and used for strobing memory write data to the registers of the PC Card when the card is configured in the memory interface mode. It is also used for writing the configuration registers. In PC Card I/O mode, this signal is used for writing the configuration registers. In True IDE mode, this input signal is not used and should be connected to VCC by the host. WAIT: The -WAIT signal is driven low by the PC Card to signal the host to delay completion of a memory or I/O cycle that is in progress. IORDY: In True IDE mode, this output signal may be used as IORDY. I/O PORT IS 16 BITS: Memory mode - The PC Card does not have a write protect switch. This signal is held low after the completion of the reset initialization sequence. XWP/ XIOIS16 66 O I/O operation - When the PC Card is configured for I/O operation pin 24 is used for the -I/O selected is 16-Bit Port (-IOIS16) function. A low signal indicates that a 16 bit or odd byte only operation can be performed at the addressed port. In True IDE mode, this output signal is asserted low when this device is expecting a word data transfer cycle.
XWE
90
I
XWAIT
81
O
13
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued) Signal Name 100-Pin Number I/O Description INPUT PORT ACKNOWLEDGE: This signal is not used in memory mode. The Input acknowledge signal is asserted by the PC Card when the card is selected and responding to an I/O read cycle at the address that is on the address bus. This signal is used by the host to control the enable of any input data buffers between the PC Card and the CPU. In True IDE mode, this output signal is not used and should be connected at the host. READY/BUSY: In memory mode, this signal is set high when the PC Card is ready to accept a new data transfer operation and held low when the card is busy. The host memory card socket must provide a pull-up resistor. At power up and at reset, the RDY/BSY signal is held low (busy) until the PC Card has completed its power up or reset function. No access of any type should be made to the PC Card during this time. The RDY/-BSY signal is held high (disabled from being busy) whenever the following condition is true: The PC Card has been powered up with +RESET continuously disconnected or asserted. I/O operation - After the PC Card has been configured for I/O operation, this signal is used as Interrupt request. This line is strobed low to generate a pulse mode interrupt or held low for a level mode interrupt. In True IDE mode, this signal is the active high Interrupt request to the host. I/O READ: This signal is not used in memory mode.This is an I/O read strobe generated by the host. This signal gates I/O data onto the bus from the PC Card when the card is configured to use the I/O interface. In True IDE Mode, this signal has the same function as in PC Card I/O Mode.
XINPACK
79
O
XRDY
88
O
XIORD
95
I
14
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued) Signal Name 100-Pin Number I/O Description I/O WRITE: This signal is not used in memory mode.The I/O write strobe pulse is used to clock I/O data on the card data bus into the PC Card controller registers when the PC Card is configured to use the I/O interface. The clocking will occur on the negative to positive edge of the signal (trailing edge). In True IDE mode, this signal has the same function as in PC Card I/O Mode STATUS CHANGED: This signal is asserted high as the BVD1 signal since a battery is not used with this product.This signal is asserted low to alert the host to changes in the RDY/-BSY and write protect states, while the I/O interface is configured. Its use is controlled by the Card config and status. In the True IDE mode, this input / output is the pass diagnostic signal in the Master/Slave handshake protocol. CARD SELECT: In True IDE mode, this signal is used for configure this device as a master or slave. When it is grounded , the device is configured as a master. When this signal is open, the device is configured as a slave. In I/O and memory mode, this signal is not used. RESET: When the pin is high, this signal resets the PC Card. The PC Card is reset only at Power up if this pin is left high or open from powerup. The PC Card is also reset when the soft reset bit in the Card Configuration Option Register is set. In the True IDE mode, this input pin is the active low hardware reset from the host.
XIOWR
92
I
BVD1 / XSTSCHG
71
I/O
XCSEL / XDS
86
I
XRESET
83
I
15
SPECIFICATION
S3F49FAX
Table 3. Signal Description for PCMCIA/IDE Interface (Continued) Signal Name 100-Pin Number I/O Description This output line is always driven to a high state in memory mode since a battery is not required for this product. BVD2/XDASP 73 I/O This output line is always driven to a high state in I/O mode since this product does not support the audio function. In the True IDE mode, this input/output is the disk active/slave present signal in the Master/Slave handshake protocol.
16
SPECIFICATION
S3F49FAX
Table 4. Signal Description for Flash Memory Interface Signal Name FD0 FD1 FD2 FD3 FD4 FD5 FD6 FD7 FRDY0 FRDY1 FALE 100-Pin Number 55 56 57 58 59 60 61 62 45 46 50 I I/O O FLASH READY: The signal is used for indicate to the controller, which flash memory is ready to accept a command. FLASH ADDRESS LATCH ENABLE: When this signal is asserted the controller can send an address to the flash memory by asserting of FWE pin. FLASH COMMAND LATCH ENABLE: When this signal is asserted, a command can be to the flash memory. FLASH READ ENABLE: This signal is asserted to enable the reading of data from the flash memory. FLASH WRITE ENABLE: When this signal is asserted , the controller can write data to the flash memory. I/O I/O Description FLASH DATA BUS[15:0]: These lines are 16-bit data lines to/from the flash memory chip.
FCLE
49
O
FRE
51
O
FWE
52
O
17
SPECIFICATION
S3F49FAX
Table 4. Signal Description for Flash Memory Interface (Continued) Signal Name FCE0 FCE1 FCE2 FCE3 FCE4 FCE5 FCE6 FCE7 FCE8 FCE9 FWP 100-Pin Number 44 43 42 41 40 39 38 37 36 35 53 I/O O O I/O I/O I/O I/O I/O I/O I/O I/O O PROTECTION OF WRITING FLASH MEMORY: Write protect of flash chips Description FLASH CHIP ENABLE: These lines are flash memory enable signal.
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SPECIFICATION
S3F49FAX
Table 5. Signal Description for Miscellaneous Part Signal Name 100-Pin Number I/O Description TEST CLOCK: The S3F49FAX contains internally in-circuit emulation block for debugger mode which use standard JTAG protocol. When the controller go into debugger mode, this signal is provided from external debugger tool. TEST MODE SELECT: In the debugger mode, this signal select test mode. This pin should be held to "1', when do not use the JTAG block. TEST DATA INPUT: In the debugger mode, this signal is used for carry data. from external debugger tool to the controller. TEST RESET: This signal should be sustained LOW first at the begging of normal operation. TEST DATA OUTPUT: In the debugger mode, this signal is used for carry data. from the controller to external debugger tool. INPUT CLOCK: This signal is system clock. OUTPUT CLOCK: This signal is system output clock. SELECT TEST MODE: Select the test mode of chip Output Internal Reset Signal Output the PLL clock signal for checking PLL operation Protect writing/erasing operation
TCK
17
I
TMS
16
I
TDI
15
I
TRST
14
I
TDO
20
O
XI XO TEST0 TEST1 TEST2 RSOUT CKOUT HWP
21 22 31 32 33 25 24 23
- -
I I/O I/O I
19
SPECIFICATION
S3F49FAX
Table 5. Signal Description for Miscellaneous Part (Continued) Signal Name VCON MODE_SET 100-Pin Number 30 29 I/O I I Description Define reference voltage for VCO Select Controller Clock mode, INPUT (high): VCO mode INPUT (low): PLL mode General Purpose Input/Output Port If you use GPIO, you should set SFR(PortFun, PortDir, PortDat)
GPIO[0:9]
42 41 40 39 38 37 36 35 25 24
I/O
PLLCAP
27
-
PLL Capacitor
20
SPECIFICATION
S3F49FAX
Table 6. Signal Description for Power Signal Signal Name VDD 100-Pin Number 13 19 34 48 54 64 PVDD1 PVDD2 GND 77 94 10 18 47 63 75 VDDA VSSA 26 28 - - Analog power supply voltage for PLL Analog ground for PLL - Ground - PCMCIA power supply voltage I/O - Description System power supply voltage
Table 7. Signal Description for USB Device Signal Name DP DN 100-Pin Number 11 12 I/O I/O I/O Positive data Negative data Description
Table 8. Signal Description for Internal NOR Flash Memory Signal Name SDATA SCLK 100-Pin Number 46 45 I/O I/O I Description Serial data for internal flash Serial clock for internal flash
21
SPECIFICATION
S3F49FAX
3
Symbol VDD VIN I IN TSTG
ELECTRICAL DATA
3.1 DC CHARACTERISTICS
Table 9. Absolute Maximum Ratings Parameter DC Supply voltage DC Input voltage DC input current Storage temperature 3.3V I/O 5.0V I/O 10 -40 to 125 Ratings - 0.3 to 4.0 -0.3 to 3.6 -0.5 to 5.5 Unit V V mA C
Table 10. Recommended Operating Conditions Symbol VDD TA DC supply voltage Temperature range Parameter Ratings 3.0 to 3.6 -25 to 85 Unit V C
Table 11. Thermal Characteristics Symbol Parameter Thermal Impedance of Samsung 100TQFP Package Value 37-70 Unit C/W
ja
22
SPECIFICATION
S3F49FAX
Table 12. D.C. Electrical Characteristics (In case of 3.3V Interface I/O) (VDD = 3.3 0.3V, TA = -25 to 85 C) Symbol VIH VIL VT VT+ VTIIH Parameter High level input voltage Low level input voltage Switching threshold Switching trigger, positive-going threshold Switching trigger, negative-going threshold High level input current Input buffer Input buffer with pulldown IIL Low level input current Input buffer Input buffer with pull-up VOH High level output voltage Type B4, B8 Type B4 Type B8 VOL Low level output voltage Type B4, B8 Type B4 Type B8 IOZ IDD IDS Tri-state output leakage current Maximum operating current Stop current VIN = VSS VIN = VDD LVCMOS Interface LVCMOS Interface LVCMOS LVCMOS LVCMOS 0.8 -10 10 -10 -60 VDD- 0.05 V 2.4 0.05 V 0.4 A mA A -30 30 10 60 10 -10 A A 1.4 2.0 Conditions Min 2.0 0.8 Typ Max Unit V V V V V
IOH = -1 mA IOH = -4 mA IOH = -8 mA IOL = 1 mA IOL = 4 mA IOL = 8 mA VOUT = VSS or VDD VDD = 3.3 V, VCON = 2.2 V
-10 45 100
10 80 150
23
SPECIFICATION
S3F49FAX
Table 13. D.C. Electrical Characteristics (In Case of 5V Interface I/O) (VDD = 5.0 0.5V, TA = -25 to 85 C) Symbol VIH VIL VT VT+ VTParameter High level input voltage Low level input voltage Switching threshold Switching trigger, positivegoing threshold Switching trigger, negativegoing threshold High level input current CMOS TTL CMOS TTL CMOS TTL CMOS TTL CMOS TTL Input buffer IIH Input buffer with pull-up Input buffer IIL Low level input current Input buffer with pull-up Type B4 Type B8 Low level output voltage Type B4 Type B8 Tri-state output leakage current Maximum operating current Stop current VIN = VSS IOH = -4 mA IOH = -8 mA IOL = 4 mA IOL = 8 mA VOUT = VSS or VDD VDD = 5.0 V, VCON = 2.2 V -10 55 200 VIN = VDD 1.5 0.8 -10 10 -10 -200 VDD-0.8 -100 100 2.45 1.45 3.0 1.8 2.0 1.1 10 200 10 -10 A A 3.5 2.0 Conditions Min 3.5 2.0 1.5 0.8 Typ Max Unit V V V V V
VOH
High level output voltage
V
VOL
0.4
V
IOZ IDD IDS
10 80 250
A mA A
24
SPECIFICATION
S3F49FAX
3.2 AC CHARACTERISTICS
Table 14. System Clock Timing Symbol TC Tlpd Thpd Parameter Clock cycle time Clock low pulse duration Clock high pulse duration Min 40 0.4Tc 0.4Tc Typ 55 Max 75 0.6Tc 0.6Tc Unit ns ns ns
Tlpd TC
Thpd
Table 15. POR(Power On Reset) Detection Level Symbol PD Parameter POR Detection Level Min 1.3 Typ 2.1 Max 2.65 Unit V
25
SPECIFICATION
S3F49FAX
4
MECHANICAL DATA
The S3F49FAX disk controller is available in a 100-pin TQFP package (Samsung part number 100-TQFP-1414).
16.00 BSC 14.00 BSC 0-7 0.127
+ 0.073 - 0.037
16.00 BSC
14.00 BSC
100-TQFP-1414
0.08 MAX
#100
#1 0.50
+ 0.07
0.20 - 0.03 0.08 MAX 0.05-0.15 (1.00) 1.00 0.05 1.20 MAX
NOTE: Dimensions are in millimeters.
Figure 3. 100-TQFP-1414 Package Dimension
0.45-0.75
26

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